1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a dummy gate electrode, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In a semiconductor device, crystal defects existing in a depletion layer and around a junction cause a leak current. The crystal defects tend to occur in a process of forming an isolation region. In a LOCOS (LOCal Oxidation of Silicon) method, for example, the crystal defects result from stress at a field oxidation. In an STI (Shallow Trench Isolation) method, the crystal defects tend to occur in a silicon substrate at the end of a trench due to stress caused by a difference in a thermal expansion coefficient between the silicon substrate and a buried oxide film. It is desired to eliminate circuit malfunctions due to the leak current and thus to improve reliability of the semiconductor device.
A technique disclosed in Japanese Laid Open Patent Application JP-Syo-60-225468 intends to provide a high-voltage field-effect semiconductor device capable of reducing a leak current. The semiconductor device has a semiconductor substrate, a device isolation insulating film formed in the semiconductor substrate, a high impurity layer formed immediately below the device isolation insulating film, a thin gate insulating film formed on a surface of an active region surrounded by the device isolation insulating film, an impurity non-injected region with a predetermined width provided near the gate insulating film along a boundary between the device isolation insulating film and the gate insulating film, source/drain regions formed in a region surrounded by the impurity non-injected region to be spaced apart from each other, and a gate metal layer formed on the gate insulating film to cover from a region between the source region and the drain region to the impurity non-injected region.
Also, the followings are known to the general public as conventional techniques intending to improve reliability of semiconductor devices.
A semiconductor device disclosed in Japanese Laid Open Patent Application JP-Heisei-3-239368 has a first gate electrode formed on an active region surrounded by an isolation insulating film provided in a semiconductor substrate, a second gate electrode formed to cover from a part of the insulating film to the active region, a drain region formed in the semiconductor substrate between the first and the second gate electrodes, and a channel stopper formed below the insulating film. The drain region and the channel stopper are formed so as to be separated from each other. The first gate electrode is electrically connected with the second gate electrode.
A semiconductor integrated circuit disclosed in Japanese Laid Open Patent Application JP-Heisei-4-254381 has a MIS-type semiconductor device in a device formation region surrounded by a field insulating film which forms an isolation region. A gate electrode of the MIS-type semiconductor device is formed to have a pattern portion extending along a boundary between the isolation region and the device formation region. A potential applied to the gate electrode is also applied to the pattern portion.